Platforms for a Future GNSS Receiver
A Discussion of ASIC, FPGA, and DSP Technologies
“Working Papers” explore the technical and scientific themes that underpin GNSS programs and applications. This regular column is coordinated by Prof. Dr.-Ing. Günter Hein.
Since introduction of the first GPS receivers more than a quarter century ago, GNSS equipment has changed profoundly – from racks of computers and 25-pound “manpacks” into tiny integrated circuit chipsets suitable for inclusion in mobile phones and other portable devices. But the evolution of GNSS form factors is far from ended. Indeed, the appearance of new GPS and GLONASS signals and the arrival of Galileo has injected new vitality into design of GNSS products. This installment of Working Papers traces the trajectory – past, present, and future – of that technological evolution.
GNSS receiver technology has changed dramatically since the first reception of a GPS signal. It evolved from complex electrical circuits — partly analog — tracking only one satellite at a time to today’s sophisticated, small multichannel receivers. The core of a modern receiver is contained in one or more highly sophisticated chips that perform all the receiver’s tasks, starting with signal processing, followed by positioning, and often ending at application processing.
The technology to build these chips is called application-specific integrated circuit (ASIC) technology. Following this approach of receiver design, a manufacturer completely designs the chip from scratch, having the maximum flexibility in the design but also facing tremendous development efforts and costs. By selling a large amount of chipsets, the manufacturer hopes to recover those development costs, enabling the company to offer affordable receivers while still making a profit. However, redesign of a receiver ASIC remains a major task and can only be afforded once every several years.
Nowadays, improvements in software and hardware technology seem to promise reductions in future receiver development costs by using field programmable gate arrays (FPGAs), digital signal processors (DSPs), or even general purpose processors to realize a complete GNSS receiver. The receiver makes use of these predefined hardware structures, which can be configured (in case of an FPGA) or programmed (in case of a processor) by means of software.
For such projects a large number of elaborate tools are available, providing the engineer with a convenient development environment. This, in turn, will lead to greater design productivity and lower development costs. Furthermore, the software approach makes it possible to run field upgrades of the receiver. The obvious question thus arises —with which technology will the future GNSS receiver be built: ASIC, FPGA, DSP, or even a general purpose central processing unit (CPU)?
In this article we try to answer this question as completely as possible by describing future GNSS hardware platforms, focusing on different techniques to realize GNSS tracking and using our background in receiver technology from the algorithmic and application points of view.
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Prof. Dr.-Ing. Günter Hein is a member of the European Commission’s Galileo Signal Task Force and organizer of the annual Munich Satellite Navigation Summit. He has been a full professor and director of the Institute of Geodesy and Navigation at the University of the Federal Armed Forces Munich (University FAF Munich) since 1983. In 2002, he received the United States Institute of Navigation Johannes Kepler Award for sustained and significant contributions to the development of satellite navigation. Hein received his Dipl.-Ing and Dr.-Ing. degrees in geodesy from the University of Darmstadt, Germany.
Stefan Wallner studied at the Technical University of Munich and graduated with a diploma in techno-mathematics. He is now a research associate at the Institute of Geodesy and Navigation at the University of the Federal Armed Forces Germany in Munich. His main topics of interest include the spreading codes and the Galileo Signal Structure.
Jong-Hoon Won received his B.S. and M.S. degrees in control and instrumentation engineering at Ajou University, Suwon, Korea. He also received his Ph.D. at the same university based on the design and development of a software-based GPS receiver and precise navigation algorithm. Since 2005, he has worked as a research associate with the Institute of Geodesy and Navigation of the University of Federal Armed Forces Munich, Germany. His current research interests are in the signal processing and navigation algorithms for GNSS receivers.
Thomas Pany has a Ph.D. in geodesy from the Graz University of Technology and a MS in Physics from the Karl-Franzens University of Graz. Currently he is working at the Institute of Geodesy and Navigation at the University of Federal Armed Forces Munich. His major areas of interest include GPS/Galileo software receiver design, Galileo signal structure and GPS science.
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